It is well known that stress in the silicon lattice of an MOS transistor in an integrated circuit (IC) increases the mobility of the charge carriers in the channel of the transistor under the gate, and hence improves the on-state drive current. There are various methods to provide stress to the active area containing the MOS transistor, including formation of a stress inducing liner in the field oxide regions adjacent to the transistors formed by shallow trench isolation (STI). STI field oxide regions are formed by etching a trench into the silicon substrate of the IC, growing a liner oxide on the trench sidewalls, and filling the trench with silicon dioxide. The liner oxide provides a small level stress to the active area adjacent to the trench. It is known that adding nitrogen to an interface between the silicon substrate at the STI sidewall and the liner oxide increases the stress in the active area, but control of the amount of nitrogen has been problematic.